Method of fabricating a dynamic random access memory (DRAM) cell capacitor using hemispherical grain (HSG) polysilicon and selective polysilicon etchback

ABSTRACT

A storage node 64 of a capacitor having increased charge storage capacity and a method for forming thereof. A doped polysilicon region 68 is formed. A thin layer of hemispherical grain polysilicon 70 is deposited over the doped polysilicon region 68. The doped polysilicon region 68 and the thin layer of hemispherical grain polysilicon 70 are etched using an etch chemistry that etches the doped polysilicon region 68 faster than the thin layer of hemispherical grain polysilicon 70 to increase the surface area of an upper surface 66 of the storage node 64.

FIELD OF THE INVENTION

This invention generally relates to semiconductor processing and morespecifically to storage capacitors for dynamic memories.

BACKGROUND OF THE INVENTION

The acquisition of sufficient charge-storage capacity in a small area isone of the most challenging design problems of Ultra Large ScaleIntegration (ULSI) Dynamic Random Access Memory (DRAM) technology. Asthe push for higher density DRAMs increases, the charge-storage deviceof each memory cell must physically fit into a smaller and smaller area.A moderate degree of success has been achieved through the use of cellstructure innovations which increase the effective storage-node areabeyond the amount allocated within each memory cell.

Several methods use hemispherical grain (HSG) polysilicon (i.e., ruggedpoly) to increase the charge storage capacity. HSG polysilicon, asdeposited, enhances the surface area by a factor of 1.6-2.2. In onemethod, a thin layer of HSG polysilicon is deposited to produce a pseudoarchipelago pattern (grain size and separation will not strictly beconstant over the area of interest) with dimensions that are far smallerthe those presently producible with current practical lithography tools.(Archipelago patterns with features less than 500 Å are possible withelectron-beam lithography, but low throughput make this processunattractive.) The HSG polysilicon 10 is deposited on a thin CVD(chemical-vapor deposition) oxide layer 12 that rests on top of a thickdoped polysilicon layer 14, as shown in FIG. 1a. The doped polysiliconlayer 14 extends through oxide layer 18 to semiconductor body 20. Anoxide etch, followed by a polysilicon etch produces a micro-villuspattern 16 as shown in FIG. 1b. A major problem with this approach isthat area enhancement is due totally to the ability to form micro villiof high aspect ratio. The inability to strictly control the HSGpolysilicon grain distribution threatens the manufacturability andreliability of such a structure. Thus, there is a need for surface areaenhancement of charge-storage nodes that is easily manufacturable,repeatable, and reliable.

SUMMARY OF THE INVENTION

Generally, and in one form of the invention, a capacitor havingincreased storage node capacity and a method of forming such a capacitorare disclosed herein. A doped polysilicon storage node is formed at thesurface of a semiconductor body. A thin layer of HSG polysilicon is thenformed over the structure. The doped and HSG polysilicon are then etchedusing an etch chemistry that selectively etches the doped polysiliconfaster that the HSG polysilicon. An etch ratio of at least 3:1 ispreferred. The etch is anisotropic and does not remove the HSGpolysilicon from the sidewalls of the storage node. As a result,U-shaped grooves are formed in the upper surface of the dopedpolysilicon storage node which increases the surface area of the storagenode, and thus increase the charge storage capacity.

An advantage of the invention is providing a capacitor having increasedstorage capacity.

A further advantage of the invention is providing a charge storage nodehaving increased surface area.

A further advantage of the invention is providing a charge storage nodehaving increased surface area that is highly reproducible, reliable andeasily fabricated.

These and other advantages will be apparent to those of ordinary skillin the art having reference to the specification in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIGS. 1a-1b are cross-sectional views of a prior art charge storagenode;

FIGS. 2a-2b are perspective and layout views, respectively, of a DRAMcell according to the invention;

FIG. 3 is a cross-sectional view of a charge storage node according tothe invention;

FIGS. 4a-4h are cross-sectional views of a charge storage node accordingto the invention at various stages of fabrication;

FIG. 5a is a perspective view of a charge storage node prior to HSGetchback;

FIG. 5b is a graph of storage node height versus area enhancementfactor;

FIG. 5c is a perspective view of a charge storage node after HSGetchback;

FIG. 6 is a graph of area enhancement factor and etch depth versus etchduration; and

FIG. 7 is a graph of I-V characteristics comparing before and after etchleakage currents.

Corresponding numerals and symbols in the different rises refer tocorresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The invention will be described in conjunction with a charge storagenode for a DRAM memory cell. However, it will be apparent to thoseskilled in the art that the invention is applicable to many technologiesdesiring increased storage capacity in a small area.

One embodiment of a DRAM cell using a charge storage node according tothe invention is shown in FIGS. 2a-b. DRAM cell 50 is a capacitor overbitline (COB) type cell. Active area 52 is formed in substrate 54.Wordline 56 extends over active area 52 to fore the gate of atransistor. Contact 58 connects bitline 60 to active area 52 on one sideof wordline 56. A local interconnect 62 is used to connect chargestorage node 64 to active area 52 on the other side wordline 56. Withthe exception of charge storage node 64, DRAM cell 50 is a conventionalDRAM cell and operates in a conventional manner.

Charge storage node 64 has increased surface area on the upper surface66, as shown in detail in FIG. 3. Charge storage node 64 includes adoped polysilicon region 68 and a thin layer of HSG polysilicon 70 onthe sidewalls of the doped polysilicon region 68. HSG polysilicon layer70 increases the surface area on the sidewalls of charge storage node 64by a factor on the order of 1.6 to 2.5. None of the originally depositedHSG polysilicon is located on the upper surface 66 of charge storagenode 64. The upper surface 66 of charge storage node 64 has U-shapedgrooves 72 which have a depth on the order of 0.1-0.3 microns. TheU-shaped grooves 72 of upper surface 66 increase the surface area by afactor on the order of 3 or greater depending on the depth and averagespacing of the U-shaped grooves 72.

The storage capacity of a capacitor is directly related to the effectivesurface area of the nodes or electrodes of the capacitor. Thus,increasing the surface area of charge storage node 64 increases thestorage capacity of a capacitor formed with charge storage node 64 asthe bottom electrode. This is extremely important for very densedevices, such as DRAMs, where the area allocated for charge storagecapacity is very small. In addition, upper surface 66 avoids theproblems of reliability, repeatability, and difficulty in manufacturingassociated with high aspect ratio structures used in prior arttechniques.

FIG. 4a shows a semiconductor body 82 having a dielectric layer 84formed thereon. Dielectric layer 84 has been patterned and etched toremove the portions where a charge storage node 64 is to be formed. Asis the case for COB cells, semiconductor body 82 may have active areas,bitlines, wordlines, and other structures (not shown) located therein.Typically, semiconductor body 82 will not yet include metal interconnectlines.

The formation of a charge storage node 64 into the structure of FIG. 4aaccording to the invention will now be described. A layer of polysiliconis deposited over the surface of the structure to a depth abovedielectric layer 84 of 0.3-0.6 microns. Preferably, the polysilicon isinsitu-doped (ISD) with phosphorous. However, the polysilicon mayalternatively be doped after deposition and/or doped with alternativedopants. The doped polysilicon layer is then patterned and etched toform the doped polysilicon region 68 of charge storage node 64, as shownin FIG. 4b. The width and length of doped polysilicon region 68 willvary by design, but may typically be in the range of 0.3 to 1 microneach.

Next, a thin layer of HSG polysilicon 70 is deposited over the structureas shown in FIG. 4c. The HSG layer 70 should be thin enough to bringabout surface area enhancement for the corresponding charge storage node64 dimensions. For high density DRAM applications, surface areaenhancement occurs when the grain size of the HSG polysilicon 70 is muchless than the dimensions of the charge storage node 64. For thin HSGlayers, the grain size and film thickness are usually on the same orderof magnitude. A grain size and film thickness on the order of 500 Å isappropriate for 256 Mb DRAM applications having approximately a 0.25 μm²storage node cross-sectional area.

Typically, HSG polysilicon layer 70 is deposited via silane (SiH₄)deposition at the amorphous silicon/polysilicon transition temperature.However, other deposition techniques may alternatively be used. HSGpolysilicon layer 70 is preferably undoped to maximize etch selectivitybetween the HSG polysilicon layer 70 and doped polysilicon region 68.

FIG. 4d shows an amplified view of the upper surface of charge storagenode 64 after HSG polysfiicon 70 deposition. The average separationbetween HSG grains 86 is key to optimization of surface areaenhancement. It is not favorable to have adjacent grains 86 in contactwith one another. As will be explained further below, an average grainseparation of 100-300 Å is desirable.

Next, a charge storage node etch is performed to enhance the surfacearea of the upper surface 66. The etch chemistry needs to be selectiveto doped polysilicon region 68 over undoped HSG polysilicon layer 70,such as a halogen based gas chemistry. An etch selectivity ratio of 3:1or greater is desired. For example, an anisotropic etch using a HBr/Cl₂etch-gas chemistry may be used. Etch process selectivity allows HSGpolysilicon layer 70 to serve as an etch mask so that the degree ofroughness of the original charge storage node surface (with HSG) may beamplified accordingly.

Referring to FIG. 4e, the doped polysilicon region 68 etches faster thanthe HSG polysilicon layer 70 causing grooves to be formed in the surfaceof the doped polysilicon region 68. The etch continues until all of theHSG polysilicon layer 70 is removed from the upper surface, as shown inFIG. 4f. This creates U-shaped grooves 72 in the upper surface having adepth on the order of 0.1-0.3. microns.

As shown in FIG. 4g, because the etch is anisotropic, the HSGpolysilicon layer 70 remains on the sidewalls of charge storage node 64.However, all of the HSG polysilicon layer 70 between charge storagenodes 64 is removed from the surface of dielectric layer 84 during thecharge storage node etch. This is necessary to electrically isolate thecharge storage nodes 64 from each other.

After the charge storage node etch, a dielectric layer is deposited,followed by the deposition of a polysilicon layer as shown in FIG. 4h.The dielectric layer may comprise an oxide-nitride-oxide tri-layer. Inorder to take advantage of the surface area enhancement, there must beenough room in the grooves 72 to accommodate both capacitor dielectric88 and top capacitor electrode 90. Accordingly, the average HSG grain 86separation before the charge storage node etch needs to be on the orderof 150 Å or larger.

FIG. 5a is a depiction of charge storage node 64 with dimensionsapproaching those needed for 256 Mb DRAM applications after depositionof thin HSG polysilicon layer 70 but prior to the etchback. A_(top) andA_(sw) are the area enhancement factors for the charge storage node 64'stop surface and sidewalls, respectively. Before etchback, A_(top) andA_(sw) are identical. The total area enhancement factor, A_(eff), isdetermined according to the following formula: ##EQU1## Assuming thatA_(top) =A_(sw) =2.25, w=0.3 μm, L=0.8 μm, and H=0.6 μm, A_(eff)according to the above equation equals 2.25. After etchback, A_(top)increases, while A_(sw) remains the same. As A_(top) increases, theheight of the charge storage node 64 can be decreased while obtainingthe same total effective area. FIG. 5b is a graph showing therelationship between the area enhancement factor of the top surface,A_(top), and the height (H) which yields a constant value of totalsurface area. For example, if the area enhancement factor, A_(top),increased to 4.2 (as a result of an etchback), the height (H) of chargestorage node 64 could be reduced to 0.5 μm while obtaining the sametotal effective area as a 0.6 μm--storage node. This is shown in FIG.5c. It should be noted that if a reduced height is not required, thefinal (post etchback) height could remain at 0.6 μm and the totaleffective area enhancement factor, A_(eff), would increase to 2.55.

FIG. 6 is a graph of how the area enhancement factor (AEF) varies as afunction of etch time using a HBr/Cl₂ etch-gas chemistry. PlanarMIS-type capacitors were used to obtain this data. The AEF firstdecreases slightly before it begin to increase. This decrease can betraced to two causes. First, the etch begins with a brief (15 sec.)breakthrough stage which occurs in CF₄. This segment of the etch is moreselective to the undoped HSG polysilicon layer. Therefore, surfaceroughness is lost during this portion of the etch and the actualstarting point of the HBr/Cl₂ etch begins with an AEF closer to 2.0.Second, because the initial grain separation in this experiment was onthe order or 100 Å, the valleys formed in the doped polysilicon portionare initially too narrow to accommodate both the capacitor dielectriclayer and the top polysilicon electrode. As the main etch proceeds, thevalleys become large enough to accommodate both the capacitor dielectricand top polysilicon electrode. FIG. 6 shows that after an etch durationof 40 seconds, an AEF of approximately 2.9 and an etch depth ofapproximately 940 Å are obtained in this example. FIG. 6 also shows thatthe AEF for a smooth polysilicon capacitor does not vary significantlywith etch duration.

FIG. 7 is a plot of leakage current versus gate voltage for etched andunetched HSG polysilicon capacitors. As can be seen in FIG. 7, thecharge storage node etch has negligible effect on the leakagecharacteristics of the storage capacitor.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

What is claimed is:
 1. A method for forming a storage node of acapacitor having increased charge storage capacity, comprising the stepsof:a. forming a doped polysilicon region; b. depositing a thin layer ofhemipherical grain polysilicon having a grain size and film thickness onthe same order of magnitude on said doped polysilicon region; and c.without masking said thin layer of hemispherical grain polysilicon,etching said doped polysilicon region and said thin layer ofhemispherical grain polysilicon using an etch chemistry that etches saiddoped polysilicon region faster than said thin layer of hemisphericalgrain polysilicon to increase an upper surface area of said storage nodewherein said etching step continues until all of said hemisphericalgrain polysilicon is removed from said upper surface of said storagenode.
 2. The method of claim 1, wherein said etch chemistry comprises ahalogen etch chemistry.
 3. The method of claim 1, wherein said etchchemistry comprises a HBr/Cl₂ etch chemistry.
 4. The method of claim 1,wherein said step of forming said doped polysilicon region comprises thestep of doping polysilicon insitu during deposition.
 5. The method ofclaim 1, wherein said doped polysilicon region is doped withphosphorous.
 6. The method of claim 1, wherein said etching step formsU-shaped grooves in an upper surface of said doped polysilicon region.7. The method of claim 6, wherein said U-shaped grooves have a depth onthe order of 0.1-0.3 microns.
 8. The method of claim 1, wherein saidthin hemispherical grain polysilicon is deposited to a thickness on theorder of 500 Å.
 9. The method of claim 1, wherein said etching step hasa selectivity of at least 3:1 between undoped polysilicon andhemispherical grain polysilicon.
 10. A method of forming a memory cell,comprising the steps of:a. forming an active area in a semiconductorbody; b. forming a polysilicon gate extending over said active area; c.forming a bitline over and insulated from said polysilicon gate, saidbitline being electrically coupled to said active area on a first sideof said polysilicon gate; and d. forming a first electrode electricallycoupled to said active area on a second side of said polysilicon gateby:i. forming a doped polysilicon node having sidewalls and an uppersurface; ii. depositing a thin layer of undoped hemispherical grainpolysilicon having a grain size and film thickness on the same order ofmagnitude on said sidewalls and said upper surface of said dopedpolysilicon node; and iii. without masking said thin layer ofhemispherical grain polysilicon etching said doped polysilicon node andsaid thin layer of hemispherical grain polysilicon with an etchchemistry having a selectivity of at least 3:1 between the dopedpolysilicon node and the thin layer of undoped hemispherical grainpolysilicon, wherein said etching step continues until all of saidhemispherical grain polysilicon is removed from said upper surface ofsaid doped polysilicon node; e. forming a capacitor dielectric over saidfirst electrode; and f. forming a second electrode over said capacitordielectric such that said first electrode, said capacitor dielectric andsaid second dielectric form a capacitor.
 11. The method of claim 10,wherein said etch chemistry comprises a halogen etch chemistry.
 12. Themethod of claim 10, wherein said etch chemistry comprises a HBr/Cl₂ etchchemistry. of said doped polysilicon node.
 13. The method of claim 10,wherein said etching step forms U-shaped grooves in said upper surfaceof said doped polysilicon node.
 14. The method of claim 13, wherein saidU-shaped grooves have a depth on the order of 0.1-0.3 microns.
 15. Themethod of claim 10, wherein said thin hemispherical grain polysilicon isdeposited to a thickness on the order of 500 Å.